1. Field
This disclosure relates generally to phase-locked loop systems, and more specifically, to a phase-locked loop system including a phase-error spreading circuit.
2. Related Art
In many systems, phase-locked loop (PLL) systems are employed to generate a reliable clock by determining a phase difference between a reference clock and a feedback clock. The phase difference between the reference clock and the feedback clock is typically converted into an up signal or a down signal, which are coupled to a charge pump. The charge pump produces signals that can be used to control the output of a voltage controlled oscillator (VCO). A clock signal derived from the VCO clock is then used as the feedback clock. The goal of the PLL is to reduce the phase difference between the reference clock and the feedback clock. With the continuing reduction in feature size of the components used to manufacture the various blocks of the PLL and other advances in system design, the PLLs need to satisfy very stringent operating parameters, such as jitter.
Traditional approaches to satisfy these stringent operating parameters, including jitter have not been tightly controllable. For example, in typical PLL systems, phase error is measured only at the positive edge of the reference clock. Any phase error correction is thus made every reference clock cycle only. This delay in effecting phase correction results in phase jitter.
Accordingly, there is a need for circuits and methods that can be used to better manage jitter, such as a phase-error spreading circuit.